1. Field of the Invention
The present invention relates to a memory device for recording information by accumulating charges in a charge accumulation layer and a memory array formed by integrating the memory devices.
2. Description of the Related Art
A conventional memory device represented by an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a flash memory has a charge accumulation layer for accumulating charges (i.e., electrons or holes) surrounded by an insulating film such as a SiO.sub.2 (silicon dioxide) film between a gate electrode and a substrate of a MOS (Metal-Oxide-Semiconductor) transistor. In the memory device, when a high voltage is applied between a source electrode and a drain electrode thereof and a high voltage is applied to the gate electrode, charges are conducted through the insulating film according to tunnel effect and accumulated in the charge accumulation layer and a difference in the number of charges accumulated is retained as a difference in information. The retained information can be read out by using the fact that the magnitude of a current flowing between the source electrode and the drain electrode changes according to the number of charges accumulated in the charge accumulation layer.
In the conventional memory device, however, the charge accumulation layer is surrounded by an insulating film of a single layer. For making the information retaining time sufficiently long, therefore, the insulating film has to be made thick so as to have a thickness in the range of, for example, approximately 10 to 20 nm. For writing and erasing information practically, therefore, a large gate voltage of at least 10 V has to be applied which results in hindering implementation of finer devices.
Furthermore, if the conventional memory device is made finer, the short channel effect occurs in the same way as the field effect transistor. It is thus expected that the conductivity of the conduction layer does not change efficiently between the case where charges are accumulated in the charge accumulation layer and the case where charges are not accumulated therein. The conventional memory device had such a problem.
Furthermore, in the conventional memory device, whereas a large gate voltage has to be applied for writing or erasing the information, even a small gate voltage causes some charge conduction and changes the number of charges accumulated in the charge accumulation layer. In a memory array formed by integrating a plurality of memory devices, therefore, the following problem also occurs: even if writing and reading information are conducted for one memory device, then some charge conduction also occurs in memory devices located in the vicinity thereof, and consequently retained information is disturbed.